1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) bit line precharge voltage generator, and more particularly, to a DRAM bit line precharge voltage generator employing the feedback of the output signal thereof.
2. Description of the Related Art
A DRAM needs a highly stable bit line precharge voltage to meet the requirement of the long refresh cycle, so the bit line precharge voltage generator must present the characteristics of easy stabilization and low-output impedance. Generally, the DRAM bit line precharge voltage generator applies a precharge voltage to the bit line of the semiconductor device, the precharge voltage having a value corresponding to half of a supply voltage, (Vcc−Vss)/2 (refer to FIG. 1).
In U.S. Pat. No. 5,255,232 (hereinafter '232), a DRAM bit line precharge voltage generator is disclosed. FIG. 1 shows a circuit diagram of the DRAM precharge voltage generator 1 in '232. The precharge voltage generator 1 comprises a first voltage divider 10 for generating a first divided-voltage signal VD1 and a second divided-voltage signal VD2, and an output circuit 12 for generating a precharge voltage Vpre in response to the first and second divided-voltage signals VD1 and VD2.
The first voltage divider 10 comprises a first PMOS transistor M1 connected between a supply voltage source Vcc and a first node S1, a first NMOS transistor M2 connected between the first node S1 and a second node S2, a second PMOS transistor M3 connected between the second node S2 and a third node S3, and a second NMOS transistor M4 connected between the third node S3 and a ground voltage source Vss. The first PMOS transistor M1 has a gate connected to the ground voltage source Vss, and thus functions as a fixed resistor having a fixed resistance. Also, the second NMOS transistor M4 has a gate connected to the supply voltage source Vcc, and thus functions as a fixed resistor having a fixed resistance. Therefore, the sizes of the first PMOS transistor M1 and the second NMOS transistor M4 could determine the voltage at the output node S4 and limit the current flowing from the supply voltage source Vcc to the ground voltage source Vss through the first voltage divider 10. On the other hand, the first NMOS transistor M2 has a gate connected to a drain thereof, and thus acts as an active resistor having a resistance that is reduced as a supply voltage (i.e., Vcc−Vss) from the supply voltage source Vcc is increased in level. Also, the second PMOS transistor M3 has a gate connected to a drain thereof, and thus acts as an active resistor having a resistance that is increased as the supply voltage from the supply voltage source Vcc is increased in level.
The output circuit 12 comprises a third NMOS transistor M5 connected between the supply voltage source Vcc and the output node S4, and a third PMOS transistor M6 connected between the output node S4 and the ground voltage source Vss. The gate of the third NMOS transistor M5 receives the first divided-voltage signal VD1 from the first node S1, and the gate of the third PMOS transistor M6 receives the second divided-voltage signal VD2 from the third node S3. The third NMOS transistor M5 has a resistance that is gradually increased as the first divided-voltage signal VD1 is decreased in level. Conversely, the third PMOS transistor M6 has a resistance that is decreased as the second divided-voltage signal VD2 is decreased in level. If the resistances of the first PMOS transistor M1 and the second NMOS transistor M4 are sufficiently large and equivalent, and the voltage of the second node S2 becomes a half Vcc voltage. In general, the sizes of the first NMOS transistor M2 and the second PMOS transistor M3 are similar to those of the third NMOS transistor M5 and the third PMOS transistor M6, respectively. When operating, the voltage of the first node S1 is equal to the voltage of the second node S2 plus the threshold voltage Vth2 of the first NMOS transistor M2. When the precharge voltage Vpre at the output node S4 drops from the half Vcc voltage, the gate-source voltage of the third NMOS transistor M5 is increased and larger than the threshold voltage of the first NMOS transistor M2, and then the third NMOS transistor M5 is turned on to increase the precharge voltage Vpre. The operation between the second PMOS transistor M3 and the third PMOS transistor M6 is similar to that between the first NMOS transistor M2 and the third NMOS transistor M5 and therefore is skipped here.
The disadvantages of the DRAM precharge voltage generator 1 are described as follows. The third NMOS transistor M5 cannot be turned off absolutely due to the gate-source voltage applied thereon close to the threshold voltage thereof, and the same situation applies to the third PMOS transistor M6. In addition, the sizes of the third NMOS transistor M5 and the third PMOS transistor M6 should be large enough to provide sufficient current to the precharge line. Therefore, a large leakage current flows from the supply voltage source Vcc to the ground voltage source Vss through the output circuit 12.
FIG. 2 is an I-V relationship diagram regarding the precharge current Ipre and the precharge voltage Vpre at the output node S4. Curve A is an I-V curve of an ideal precharge voltage generator, in which a large precharge current is provided to recover the precharge voltage back to the half Vcc voltage when the precharge voltage deviates from the half Vcc voltage. That is, Curve A shows a better capability to suppress the precharge voltage deviation. However, Curve B, the I-V curve of the DRAM precharge voltage generator 1, shows that the deviated precharge voltage cannot recover until it achieves a larger deviation, e.g., Vd. As a result, the precharged voltage Vpre generated by the DRAM precharge voltage generator 1 presents a larger deviation.
As shown in FIG. 3, U.S. Pat. No. 6,265,858 (hereinafter '858) discloses a voltage-adjusting circuit functioning as a DRAM bit line precharge voltage generator. The voltage-adjusting circuit 2 comprises a reference voltage-generating circuit 20, a comparing circuit 21, and an output circuit 22. The reference voltage-generating circuit 20 comprises first and second transistors QP10, QP11, first and second resistors R10, R12, and a variable resistor R11. The first and second transistors QP10, QP11 are substantially equivalent in size and are of a diode PMOS type, and the first and second resistors R10, R12 have resistances substantially higher than that of the variable resistor R11. The first resistor R10 and the second resistor R12 also have substantially equivalent resistances. The comparing circuit 21 comprises first and second differential amplifiers DA1 and DA2. The first differential amplifier DA1 has first and second inputs coupled to a first node N10 and a precharge voltage Vpre. The first differential amplifier DA1 compares a first reference voltage Vref1 at an inverted terminal with the precharge voltage Vpre, from a first output terminal 50 at a non-inverted terminal and generates a first control signal CS1. The second differential amplifier DA2 has first and second inputs coupled to a second node N11 and the precharge voltage Vpre. The second differential amplifier DA2 compares a second reference voltage Vref2 at an inverted terminal with the precharge voltage Vpre at a non-inverted terminal and generates a second control signal CS2. The output circuit 22 comprises a third transistor QP12 of the PMOS type and a fourth transistor QN10 of the NMOS type coupled in series between the supply voltage source Vcc and the ground voltage source Vss, and is controlled according to the first and second control signals CS1, CS2. The gate electrode of the third transistor QP12 receives the second control signal CS2, whereas the gate electrode of the fourth transistor QN10 receives the first control signal CS1. First electrodes of the third and fourth transistors QP12, QN10 are coupled to the supply voltage source Vcc and the ground voltage source Vss, respectively. Second electrodes of the third and fourth transistors QP12, QN10 are commonly coupled at a third node N12 to the precharge voltage Vpre. In operation, the first reference voltage Vref1 of Vcc/2+ΔV is applied to the first node N10, and the second reference voltage Vref2 of Vcc/2−Δ V is applied to the second node N11. If the precharge voltage Vpre is less than the first reference voltage Vref1 and larger than the second reference voltage Vref2, the third transistor QP12 and the fourth transistor QN10 are both transited to “OFF” state. Thus, the precharge voltage Vpre is not varied. If the precharge voltage Vpre is less than the second reference voltage Vref2, the third transistor QP12 and the fourth transistor QN10 are transited to “ON” state and “OFF” state, respectively. As a result, the current flows to the third node N12 through the third transistor QP12, thereby stably maintaining the level of the precharge voltage Vpre. Alternatively, when the level of the precharge voltage Vpre is larger than the first reference voltage Vref1, the first and second control signals CS1, CS2 are transited to “HIGH” level. Accordingly, the third transistor QP12 and the fourth transistor QN10 are transited to “OFF” state and “ON” state, respectively. As a result, the current flows to the ground voltage source Vss via the fourth transistor QN10, thereby stably maintaining the level of the precharge voltage Vpre.
FIG. 4 shows a relationship diagram regarding the precharge current Ipre and the precharge voltage Vpre at the third node N12. A dead zone exists between Vref2 and Vref1, i.e., there is no leakage current (i.e., Ipre) flowing through the third transistor QP12 or the fourth transistor QN10 when the precharge voltage Vpre is within the dead zone. In comparison with Curve B of FIG. 2, the I-V curve of FIG. 4 is sharper when the precharge voltage Vpre deviates from half Vcc and out of the dead zone. However, an unstable issue may occur in the voltage-adjusting circuit 2. The circuit portion comprising the first differential amplifier DA1 and the fourth transistor QN10 equivalently forms an RC circuit, and the RC circuit contributes a pole; similarly, another pole is formed by the second differential amplifier DA2 and the third transistor QP12. From the view of feedback control theory, two poles are involved in the voltage-adjusting circuit 2 that utilizes the precharge voltage Vpre as a feedback signal and the locations of the two poles in the s-plane have to be designed carefully to avoid oscillation of the precharge voltage Vpre.
FIG. 5 illustrates the Bode gain plots and Bode phase plots of two feedback systems. For a stable feedback system, its gain drops below 0 dB with a phase above negative 180 degrees at the gain crossover frequency Wgc (refer to Curves C and C′). However, for an unstable feedback system, its phase drops below negative 180 degrees before its gain drops blow 0 dB at the gain crossover frequency Wgc, (refer to Curves D and D′).
In general, for high-density DRAMs, e.g., capacity above 128 Mb, the MOS transistors used in the output circuit 22 of the voltage-adjusting circuit 2 are large enough to drive the bit line. That is, the equivalent capacitances of the MOS transistors are also large enough, and thus, poles contributed by large capacitances will be located at low-frequency regions in the frequency spectrum. A low-frequency pole introduced would cause the Bode gain plot of a feedback system to begin to drop at a lower frequency, and makes a lower gain crossover frequency (refer to FIG. 5), in which the feedback system becomes stable. Therefore, there is no stable issue for the voltage-adjusting circuit used for high-density DRAMs. However, for low-density DRAMs, e.g., capacity below 16 Mb, some failure modes that result in leakage current in the bit line are caused by current manufacturing process technology. To compensate for the leakage current in the low-density DRAMs, the MOS transistors used in the voltage-adjusting circuit 2 have to be designed with high driving capacity (i.e., large size), or the small equivalent RC value that contributes high-frequency poles will be apt to cause the voltage-adjusting circuit 2 to be unstable.